1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to dynamic random access memories (referred to as DRAM hereinafter) comprising capacitor portions (stacked capacitor cell) having stacked structures.
2. Description of the Background Art
DRAM is already well known. FIG. 7 is a block diagram showing one example of an entire structure for a conventional DRAM.
Referring to FIG. 7, the DRAM comprises a memory cell array 1000 including a plurality of memory cells as storage portions, a row decoder 2000 and a column decoder 3000 connected to address buffers for selecting an address of a memory cell, and an input/output interface portion including sense amplifiers connected to an input/output circuit. The plurality of memory cells as the storage portions are provided in matrix of a plurality of rows and columns. Each memory cell is connected to a corresponding word line connected to the row decoder 2000 and to a corresponding bit line connected to the column decoder 3000, which constitutes the memory cell array 1000. As the row decoder 2000 and the column decoder 3000 respectively receive externally applied row address signal and column address signal to select a single word line and a single bit line for selecting a memory cell. Data is written into the selected memory cell or the data stored in the memory cell is read out. Instructions of the data writing/reading are given by a writing/reading control signal applied to a control circuit.
Data is stored in the memory cell array 1000 of N (=n.times.m) bits. Address information of a memory cell to which writing/reading is performed is stored in the row and the column address buffers, and memory cells of m bits are coupled to the sense amplifiers through bit lines by selecting a particular word line (selection of a single word line among n number of word lines) by means of the row decoder 2000. Then, one of the sense amplifiers is coupled to the input/output circuit by selecting a particular bit line (selection of a single bit line among m number of bit lines) by means of the column decoder 3000, whereby reading or writing is performed in accordance with instructions of the control circuit.
FIG. 8 is an equivalent circuit showing a memory cell 100 of a DRAM illustrated for explaining a writing/reading operation of a memory cell. According to the drawing, one memory cell 100 comprises a pair of a field effect transistor Q and a capacitor Cs. A gate electrode of the field effect transistor Q is connected to a word line 200, one of source/drain electrodes is connected to one electrode of the capacitor Cs, and the other of the source/drain electrodes is connected to a bit line 300. In data writing, the field effect transistor Q is rendered conductive by an application of a predetermined voltage to the word line 200, so that electric charges applied to the bit line 300 are stored in the capacitor Cs. On the other hand, in data reading, the field effect transistor Q is rendered conductive by the application of a predetermined voltage to the word line 200, so that the electric charges stored in the capacitor Cs are read out through the bit line 300.
FIG. 9 is a partial plan view showing a plane arrangement of a memory cell of a conventional DRAM. FIG. 10 is a sectional view taken along a line X--X of FIG. 9.
A structure and an operation of a conventional memory cell will be described in the following with reference to these drawings.
One memory cell is structured by an n channel MOS transistor and a capacitor formed on a major surface of a p type silicon substrate 1. The n channel MOS transistor comprises a gate electrode 7, and n.sup.+ impurity diffusion regions 4 and 5 which will be source and drain regions. The n.sup.+ impurity diffusion regions 4 and 5 are formed spaced apart from each other on the major surface of the p type silicon substrate 1 so as to define a channel region with a part of the major surface of the silicon substrate 1 serving as a channel surface. The gate electrode 7 is formed on the channel region through a gate oxide film 6. An active region 20 formed of the n.sup.+ impurity diffusion regions 4 and 5 and the channel region is isolated from the environment through an isolating field oxide film 3. A p.sup.+ impurity diffusion region 2 is formed under the field oxide film 3. The gate electrode 7 is formed as a word line. The capacitor is connected to the n.sup.+ impurity diffusion region 4 through a contact hole 17. The capacitor is formed of a storage node 8 connected to the n.sup.+ impurity diffusion region 4 and a cell plate 10 formed on the storage node 8 through a capacitor dielectric film 9. A bit line 12 is connected to the n.sup.+ impurity diffusion region 5 through a contact hole 16. An interlayer insulating film 11 is formed between the bit line 12, the word line 7 and the cell plate 10.
Writing operation using a memory cell structured as the foregoing will be described. First, in a writing operation of "1", a predetermined voltage is applied to the n.sup.+ impurity diffusion region 5 through the bit line 12. Then, the n channel MOS transistor is turned on by an application of a predetermined voltage to the gate electrode 7. With the bit line 12 being at the High level, electrons in the n.sup.+ impurity diffusion region 4 are drawn out to the n.sup.+ impurity diffusion region 5, raising a potential of the n.sup.+ impurity diffusion region 4 to be the same as that of the n.sup.+ impurity diffusion region 5. As a result, positive electric charges are stored in the storage node 8 connected to the n.sup.+ impurity diffusion region 4. This state is stored as the data "1" in the memory cell.
In writing operation of "0", the potential of the n.sup.+ impurity diffusion region 5 is set to the Low level. The n channel MOS transistor is turned on by an application of a predetermined voltage to the gate electrode 7. At this time, since the potential of the n.sup.+ impurity diffusion region 4 is higher than the potential of the n.sup.+ impurity diffusion region 5, electrons are injected from the n.sup.+ impurity diffusion region 5 to the n.sup.+ impurity diffusion region 4, causing the potential of the n.sup.+ impurity diffusion region 4 to fall. As a result, the positive electric changes are drawn out from the storage node 8. This state is stored as the data "0" in the memory cell.
The cell plate 10 usually has a potential (1/2) Vcc level if a power supply voltage is represented as Vcc. In a reading operation, a predetermined voltage is applied to the gate electrode 7 after the bit line 12 is applied to the (1/2) Vcc level, so that the n channel MOS transistor is turned on. As a result, the electric charges stored in the storage node 8 move to the bit line 12 through the n.sup.+ impurity diffusion regions 4 and 5. At this time, in a state where the data "1" is stored in the storage 8, a potential of (1/2) Vcc+.alpha. appears on the bit line 12, and in a state where the data "0" is stored, a potential of (1/2) Vcc-.alpha. appears on the bit line 12.
In recent years, as the manufacturing technique improves, attempts have been made in integrating and miniaturizing a memory cell of a DRAM semiconductor memory device. As a memory cell is more miniaturized, however, a capacity of each capacitor tends to be decreased. If the capacity of the capacitor is decreased, in the case of reading information stored in a memory cell, that is, when the bit line 12 is applied to a level of (1/2) Vcc beforehand, and a potential of the bit line 12 changes to a level of (1/2) Vcc.+-..alpha. according to the amount of electric charges stored in the storage node 8, a change .alpha. of the potential becomes smaller. Therefore, a reading margin for data is reduced, so that data is read out erroneously. Accordingly, it is preferable that the capacitor formed of the storage node 8, the capacitor dielectric film 9 and the cell plate 10 is formed so as to have a capacity as large as possible to obtain a larger reading margin.
In a memory cell having such structure as shown in FIG. 10, however, a plane area of the storage node 8 is limited due to the bit line 12. More specifically, in this structure, the thick interlayer insulating film 11 should be formed between the bit line 12 and the capacitor portion in order that the bit line 12 is formed in an upper layer portion of the capacitor portion formed of the storage node 8 and the cell plate 10. Therefore, a margin in a lateral direction is necessary between the cell plate 10 and the contact hole 16 through which the bit line 12 is connected to n.sup.+ impurity diffusion region 5, which limits a plane area of the storage node 8 according to the cell plate 10. Accordingly, it is difficult to increase a capacity of a capacitor.
In order to solve the above described problems, a memory cell of a DRAM having a stacked capacitor cell on a bit line has been proposed. FIG. 11 is a partly sectional view showing a memory cell of a DRAM having a stacked capacitor cell on a bit line described in "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-line Structure" IEDM (International Electron Devices Meeting) 1988, pp. 596-599. The memory cell has a structure of placing a bit line in a lower portion of a capacitor portion. FIG. 12 is a plan view thereof. FIG. 11 shows a section taken along a line XI--XI of FIG. 12. In the drawing, gate electrodes 7 which are also used as word lines are formed spaced apart through gate oxide films 6 on a silicon substrate 1. One and the other impurity diffusion regions 4 and 5 are formed spaced apart as source/drain regions through the gate electrodes 7. A bit line 12 is formed so as to be connected to the impurity region 5. The bit line 12 is formed so as to intersect with a word line 7. An interlayer insulating film 15 is formed between the word line 7 and the bit line 12. A storage node 8 is formed through the interlayer insulating film 11 above the bit line 12. The storage node 8 is formed so as to be electrically in contact with the impurity region 4. A cell plate 10 is formed so as to be opposed to the storage node 8 through a capacitor dielectric film 9. Since the bit line 12 is formed under the storage node 8 and the cell plate 10 as the capacitor portion, an active region 20 is disposed diagonal to the bit line 12 and the word line 7.
In the structure shown in FIG. 11, the storage node 8 and the cell plate 10 can be formed to extend above the contact portion at which the bit line 12 is connected to the impurity region 5. Therefore, a plane area of the capacitor portion can be enlarged, thus making it possible to increase a capacity of a capacitor.
The active region 20 has a complicated configuration as shown in FIG. 12 because of a structure of a bit line being under a stacked capacitor cell. More specifically, opposite end portions of the active region 20 have a configuration bent along a direction of the bit line. This means that a complicated pattern should be used in order to form an isolation region for isolating a plurality of active regions. Accordingly, a complicated pattern layout should be employed in order to structure a bit line embedded type stacked capacitor cell.